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Question No. 12
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Marks - 10
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PRAM stands for…….
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Options
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Programmable Random Access Memory.
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Parallel Random Access Memory.
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Parallel Random Access Machine.
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None of the above.
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Question No. 13
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Marks - 10
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Synchronization of all PE’s in an SIMD computer is done by using…….
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Options
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Hardware
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Software
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Firmware
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Both a. and b.
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Question No. 14
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Marks - 10
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. Parallelism can be achieved using …….
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Options
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Hardware
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Software
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Both hardware and software.
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It can not be achieved using hardware or software.
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Question No. 15
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Marks - 10
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. Network routing algorithms could be ……
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Options
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Static only
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Dynamic only
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Both static and dynamic.
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Depends on network user.
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Question No. 16
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Marks - 10
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Network scalability refers to ……
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Options
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The ability of a network to be modularly expandable with a scalable performance with increasing machine resources.
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The machine data transfer rate, in terms of M bytes /s transmitted through the network.
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The worst case time delay for a unit message to be transferred through the network.
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Implementation costs such as those for wires, switches, connectors, arbitration and interface logic.
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Question No. 17
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Marks - 10
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Base line network is an example of ….
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Options
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Static connection network.
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Dynamic connection network.
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It depends on the design.
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None of the above.
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Question No. 18
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Marks - 10
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Crossbar network is an example of ……
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Options
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Static connection network.
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Dynamic connection network.
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It depends on the design.
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None of the above.
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Question No. 19
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Marks - 10
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Which of the following are speedup performance laws?
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Options
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Amdahl’s law for a fixed work load.
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Fixed –load speedup.
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Amdahl’s law revisited.
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All the above.
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Question No. 20
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Marks - 10
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Which of the following are scalability metrics?
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Options
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Machine size.
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Clock Rate.
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I/O demand
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All the above
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Question No. 21
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Marks - 10
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. Instruction level parallelism could be achieved through……
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Options
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Instruction Pipelining.
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Vector Processing.
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Array Processing
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Multi Processor Architecture.
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Question No. 22
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Marks - 10
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. Which of the following is the fastest device in terms of speed?
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Options
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Cache Memory
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CPU Registers
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Main Memory
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Disk Storage
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Question No. 23
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Marks - 10
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Cache Locality of references refers to which of the following?
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Options
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Temporal Locality
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Sequential Locality
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Both a. and b.
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None of the above.
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Question No. 24
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Marks - 10
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Cache hit ratio is?
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Options
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Number of times data found in cache / Total number of access.
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Number of times data not found in cache / total number of access.
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Number of times data found in RAM/ total number of access.
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Number of times data found in hard disk/ total number of access.
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Question No. 25
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Marks - 10
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Which techniques are examples of virtual memory?
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Options
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Demand paged memory management.
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Segmented memory management.
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Segmented paged memory management
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a. and b. only.
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Question No. 26
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Marks - 10
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Virtual memory could be achieved using which of the memory device?
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Options
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Cache memory
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Main memory
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CPU Register
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Secondary Memory
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Question No. 27
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Marks - 10
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Which is the fastest memory replacement technique?
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Options
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FCFS
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LRU
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OPT
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Depends on demand of size and order.
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Question No. 28
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Marks - 10
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Which of the followings are cache addressing models?
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Options
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Physical address caches.
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Virtual address caches.
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Both a. and b.
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None of the above.
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Question No. 29
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Marks - 10
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In which of the cache mapping scheme, word size of the cache is smallest?
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Options
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Direct mapping
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Associative mapping
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Set associative mapping
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In all the above cases, word size of the cache is same
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Question No. 30
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Marks - 10
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Cache coherence may occur in …..
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Options
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Multi-computer System.
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Multiprocessor Systems.
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Single Processor Systems.
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Both a. and b.
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Question No. 31
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Marks - 10
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Cache coherence is the problem in which…..
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Options
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Duplicate data is in different caches of processors in multiprocessor systems.
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Duplicate data in cache and in RAM.
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Duplicate data in cache, RAM and Hard Disk.
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All the above.
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Question No. 32
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Marks - 10
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Write-Through Caches applies the technique……
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Options
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Whenever there is modification in cache data, in main memory data modification will be finally once with same value which is finally modified in cache.
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Whenever there is modification in cache data, simultaneously in main memory data modification will occur.
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There is no relation of data modification of cache and main memory.
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It varies from processor to processor.
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Question No. 33
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Marks - 10
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Write-Back Cache applies the technique…….
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Options
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Whenever there is modification in cache data, in main memory data modification will be finally once with same value which is finally modified in cache.
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Whenever there is modification in cache data, simultaneously in main memory data modification will occur.
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There is no relation of data modification of cache and main memory.
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It varies from processor to processor.
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Question No. 34
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Marks - 10
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What is the basic unit in store-and-forward routing?
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Options
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Input/ Output stream.
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Packet.
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Byte.
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Message.
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Question No. 35
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Marks - 10
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Masking instruction is an instruction of which category?
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Options
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Pipeline Instruction
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Vector Instruction
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Scalar Instruction
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Array Instruction
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Question No. 36
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Marks - 10
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DEC VAX 9000 is a….
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Options
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Mainframes.
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Mini Super Computer.
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Mini Computer.
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Multi Computer Architecture.
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Question No. 37
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Marks - 10
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Multi-pipelining could be achieved in ….
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Options
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Multi- Processor Systems.
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Multi-Computer System.
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Super Computer
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Mainframe
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Question No. 38
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Marks - 10
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Label-1 cache may be in ….
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Options
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Inside processor chip.
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Outside processor chip and on board.
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A part of the RAM.
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A part of the hard disk.
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Question No. 39
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Marks - 10
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Master-slave architecture is associated with…
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Options
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Multi-processor architecture.
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Multi-Computer architecture.
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Multi level cache coherence.
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All the above.
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Question No. 40
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Marks - 10
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Using Flynn's taxonomy, the various architectures can be divided into categories.
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Options
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3
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4
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5
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6
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