There are four questions in this assignment, which carries 80 marks. Rest 20 marks are for viva voce. You may use illustrations and diagrams to enhance the explanations. Please go through the guidelines regarding assignments given in the Programme Guide for the format of presentation. Answer to each part of the question should be confined to about 300 words.
1. (Covers Block 1)
(a) Perform the following arithmetic operations using binary signed 2’s complement notation for integers. You may assume that the maximum size of integers is of 8 bits including the sign bit. (Please note that the numbers given here are in decimal notation)
i) Add – 128 and 120
ii) Subtract 124 from –99
iii) Add 64 and 61
Please indicate the overflow if it is occurs. Also write, how you have identified the overflow. (3 Marks
(b) Convert the hexadecimal number: ( FAEBDC)h into equivalent binary, octal and decimal. (1 Marks)
(c) Convert the following string into equivalent “UTF 16” code – "You may assume that Hindi swar starts with अ" Are these UTF 16 codes similar as that used in ASCII? (2 Marks)
(d) Use a Karnaugh's map to design a circuit that takes four input bits and produces one output bit. The output bit is 0 if the first and fourth input are same else it is 1. (2 Marks)
(e) An 8 bit data 01101101 after transmission is received as 01001101. Explain how SEC code will detect and correct this problem. (3 Marks)
(f) Design a two bit counter (a sequential circuit) that counts from 00 to 10 only. Thus, the counter states are 00, 01, 10, 00, 01, .... You should show the state table, state diagram, the k-map for circuit design and logic diagram of the resultant design using D flip-flop or J-K flip flop. (5 Marks) 5
(g) Explain the double precision floating point IEEE 754 representation. Represent the number (124.0625)10 using IEEE 754 single precision and double precision representations. (4 Marks)
2. (Covers Block 2)
(a) A RAM has a capacity of 8192K having the word size of 16 bits and supports byte addresses only.
(i) How many data input and output lines does this RAM need? Explain your answer.
(ii) How many address lines will be needed for this RAM? Explain. (2 Marks)
(b) A computer has 1MB RAM and has word size of 16 bits. It has cache memory having 16 blocks with a block size of 32 bits. Explain how a main memory address will be mapped to a cache address, if
(i) Direct cache mapping is used
(ii) Associative cache mapping is used
(iii) Two way set associative mapping scheme is used. (4 Marks)
(c) Compare and contrast the features of Interrupt driven I/O with that of DMA. Which I/O technique will be preferable in the following situations. Give justification in support of your answer.
(i) Data is to be transferred from a very high speed device having high volume data.
(ii) Small volume of data transferred asynchronously. (4 Marks)
(d) Explain the term FAT in the context of disk operating system. What will be the size of a disk and its FAT, if a disk has 64 tracks with each track having 16 sectors and size of each sector is 512 byte? You may take the cluster size as 4 sectors. (2 Marks)
(e) Explain the characteristics of at least two portable secondary/tertiary storage devices. (2 Marks)
(f) Define each of the following terms. Also explain their use/advantage, if needed. (Word limit for answer of each part is 50 words ONLY)
(i) Access time on magnetic disks
(ii) Backup devices
(iii) Scanner resolution
(iv) LCD and its types
(v) AGP in the context of video card interfaces
(vi) Colour Depth (6 Marks) 6
3. (Covers Block 3)
(a) A hypothetical machine has 22 registers. Out of these 6 registers are used as segment registers. Assume that the machine uses segment registers to find physical address in the similar way as is done in 8086 processor. Remaining 16 registers are general purpose registers. All the registers and memory word for the machine are of 16 bits. The machine has 1 M Word RAM. An instruction of the machine is of 32 bits which includes opcode - 5 bits, addressing mode specification - 3 bits and remaining bits for specifying the operand addresses. Each instruction contains at most two operand addresses - at most one memory operand and remaining register operand(s). What would be the size of memory address, if direct addressing is used? What would be the size of the direct register operand? The machine is to be used for calculations involving arrays and floating point numbers. Design five different types of addressing modes for this machine. Give justification of the selection of every addressing mode. (4 Marks)
(b) Assume that the machine as stated in part (a) has named 5 of its general purpose registers based on their possible role in instruction execution as Program Counter (PC), Accumulator (AC), Memory Address Register (MAR), Instruction Register (IR) , Data Register (DR) and Flag registers (FR). To execute an instruction of the machine that has a direct memory operand and a register operand, the memory operand is first brought into the DR register and the register operand is transferred to AC register. The result of the operation is stored in the AC register. One of the instruction of the machine is given below: ADD R1, X // this instruction adds the operand stored in Register R1 and memory location X. The result is stored in the AC register. Write and explain the sequence of micro-operations that are required to fetch and execute this instruction. Make and state suitable assumptions, if any. (5 Marks)
(c) Assume that you have a machine as shown in section 3.2.2 of Block 3 having the micro-operations as given in Figure 10 on page 62 of Block 3. Consider that R1 and R2 both are 8 bit registers and contains 1010 0011 and 11001011 respectively. What will be the values of select inputs, carry-in input and result of operation (including carry out bit) if the following micro-operations are performed? (For each micro-operation you may assume the initial value of R1 and R2 as given above)
(i) Subtract R2 from R1
(ii) AND of R1 and R2
(iii) Shift right R1 twice
(iv) Add R1 and R2 with carry (2 Marks) 7
(d) How does a Micro-programmed control Unit will control the execution of an instruction. Explain with the help of an addition instruction. (3 Marks)
(e) Explain with the help of a diagram how does RISC Instruction pipelining work. Also explain how RISC instruction pipeline can be optimised. (3 Marks)
(f) Assume that a RISC machine has 128 registers out of which 16 registers are reserved for the Global variables and 16 for Instruction related tasks. This machine has been designed to have 12 registers for storing four input parameters, four output parameters and four local variables for a subroutine call. Explain with the help of a diagram, how the overlapped register window can be implemented in this machine for procedure calls. You must explain how the parameters will be passed, if a subroutine calls another subroutine. (3 Marks)
4. (Covers Block 4)
(a) Write a program in 8086 assembly Language (with proper comments) to count the number of alphabets 'a', 'e' and 'o' (irrespective of lower or upper case) in a strings. For example, in case the strings is: "ABaDEFeHIO" the count of 'a' will be 2, 'e' is 2 and 'o' is 1. You may assume that string is available in the memory and is of length 10. Make suitable assumptions, if any. (8 Marks)
(b) Write a program in 8086 assembly language that accepts a 2 digit input from the keyboard (as ASCII input) into packed BCD number. The packed BCD number may be stored in memory. (6 Marks)
(c) Write a simple near procedure in 8086 assembly language that receives an ASCII digit as parameter. It returns 1 if the ASCII digit is 'Z' else it returns 0. Make suitable assumptions, if any.
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University: IGNOU Year: 2015